1. Field of the Invention
The present invention relates to a polishing liquid for polishing metals and a method of polishing using the same. In particular, the invention relates to a polishing liquid for metals, which is suitably used in production of semiconductor devices and to a method of polishing using the polishing liquid.
2. Description of the Related Art
In the development of semiconductor devices exemplified by semiconductor integrated circuits such as large scale integration circuits (hereinafter also referred to as “LSI circuits”), increased density and integration through refining and lamination of wirings have been demanded in recent years in order to decrease the size and increase the operation speed of semiconductor devices. For this purpose, various techniques such as chemical mechanical polishing (hereinafter also referred to as “CMP”) have been used. CMP is a method used in polishing a thin insulating film (e.g., SiO2 film) or a metal thin film used for wiring in the production of semiconductor devices, to smoothen a substrate or to remove an excess amount of a metal thin film during formation of wirings (see, for example, U.S. Pat. No. 4,944,836).
A polishing liquid for metals (hereinafter may also be referred to as “metal-polishing liquid”) used in CMP generally includes abrasive grains (e.g., of alumina) and an oxidizing agent (e.g., hydrogen peroxide). The mechanism of CMP is considered to be as follows: the oxidizing agent oxidizes the surface of metal to form an oxide film, and the resultant oxide film is removed by the abrasive grains (see, for example, the Journal of the Electrochemical Society, 1991, Vol. 138, No. 11, pp. 3460 to 3464).
However, when chemical mechanical polishing (CMP) is conducted using a metal-polishing liquid containing such solid abrasive grains, scratches may be caused by polishing, or phenomena may occur such as excessive polishing (thinning) of the entire polished surface, excessive polishing of only a center portion of a polished metal surface resulting in dish-like subsidence of the surface (dishing) such that the polished metal surface is not planar, or dish-like subsidence (erosion) at plural metal wiring surfaces caused by excessive polishing of insulating material between the metal wirings. Furthermore, when a metal-polishing liquid containing solid abrasive grains is used in a cleaning process that is normally performed to remove any polishing liquid remaining on a polished semiconductor surface, the cleaning process is complicated and, furthermore, in order to dispose of the liquid after the washing (waste liquid), the solid abrasive grains need to be sedimented and separated, causing problems in terms of increased costs.
In order to address the problems in the conventional art, a method, for example, of polishing a metal surface using a combination of an abrasive-free polishing liquid and dry etching has been disclosed (see, for example, the Journal of the Electrochemical Society, 2000, Vol. 147, No. 10, pp. 3907 to 3913). As an abrasive grain-free metal-polishing liquid, a metal-polishing liquid including, for example, hydrogen peroxide, malic acid, benzotriazole, ammonium polyacrylate and water, and a method of polishing with the same have been disclosed (see, for example, Japanese Patent Application Laid-Open (JP-A) No. 2001-127019). According to the polishing methods described in these documents, projected portions of a metal film of a semiconductor substrate are selectively polished away by CMP while the metal film remains in concave portions to provide a desired conductor pattern, but there is the problem that a sufficient polishing rate is difficult to achieve because CMP in this case proceeds by means of friction with a significantly mechanically softer polishing pad than in the case of the conventional solid abrasive grain-containing liquid.
As wiring metals, hitherto, tungsten and aluminum have been generally used in the interconnect structure. However, in order to achieve higher performance, LSIs that use copper, which has lower wiring resistance than these metals, have been developed. As a process for wiring copper, for instance, a damascene process disclosed in JP-A No. 2-278822 is known. Furthermore, a dual damascene process in which a contact hole and a wiring groove are simultaneously formed in an interlayer insulating film and a metal is embedded in both of the hole and the groove is in wide use. As a target material for such copper wiring, a copper target having high purity of five ninths or more has been used. However, recently, as wirings are miniaturized to realize further densification, the conductivity and electric characteristics of the copper wiring require improvement; accordingly, a copper alloy in which a third component is added to high-purity copper is under study. Simultaneously, a high-performance metal-polishing means that can exert high productivity without contaminating the high-precision and high-purity material is in demand.
Furthermore, recently, in order to improve productivity, wafer diameter is enlarged when producing LSIs. At present, a diameter of 200 mm or more is generally used, and production at a magnitude of 300 mm or more has also been started. As wafer diameter is increased in this way, a difference in polishing speed tends to occur between a central portion and a peripheral portion of the wafer; accordingly, achievement of uniformity of polishing is becoming a pressing concern.
As a method of chemically polishing copper or a copper alloy without using a mechanical polishing procedure, a method of utilizing a chemical dissolution action is known (see, for example, JP-A No. 49-122432). However, methods of chemical polishing merely relying on chemical dissolution result in problems in planarity such as dishing (dish-like concave), even more so than CMP in which projected portions of the metal film are selectively polished both chemically and mechanically.
Furthermore, an aqueous dispersion for chemical mechanical polishing, which contains an organic compound that prevents the polishing pad from deteriorating, has been disclosed (see, for example, JP-A No. 2001-279231). However, even when the polishing aqueous dispersion is used, there remains a risk that the dishing phenomenon may occur whereby the metal of a wiring portion is excessively polished to cause a dish-like concavity.
For the purpose of planarizing a surface to be polished, a processing liquid containing a chelating agent selected from iminodiacetic acid and salts thereof, which is useful in modifying the surfaces of wafers (see, for example, Japanese National Phase Publication No. 2002-538284) and a CMP composition containing an α-amino acid (see, for example, Japanese National Phase Publication No. 2003-507894) have also been proposed.
Generally, a copper wiring is polished at high speed, and then tantalum or an alloy thereof often used as a barrier metal of a copper wiring, and copper, are polished precisely to planarize the region in the proximity of the wiring. Accordingly, realization of a polishing liquid that can selectively polish copper over tantalum (hereinafter referred to as Cu/Ta selectivity) is currently desired, whereby copper is easily polished away while tantalum is hardly polished away when the copper polishing is complete.
In conventional polishing methods, however, polishing for an excessively long time is carried out in a second polishing step so that a conductor film does not remain on a wafer. In the polished surface after the second polishing step, therefore, dishing occurs, that is, the phenomenon whereby the surface of the conductor film in a portion corresponding to a wiring groove subsides relative to the surface of a barrier metal film.